1. Field of the Invention
The present invention relates to a semiconductor device with an internal booster and a structure for detecting a boosted potential, and more specifically, to improvements in a connecting structure for connecting a negative potential to a resistor film in a raised potential measuring circuit in a semiconductor device.
2. Background Art
In a semiconductor memory device, such as an EEPROM, requiring a high voltage for writing and erasing data from memory cells, a positive or negative supply voltage must be raised and the raised voltage must be measured to see whether or not the supply voltage has been raised to a desired voltage.
FIG. 4 is a block diagram showing a raised potential measuring circuit. A voltage generated by a booster I or a booster II is connected to a resistance film 35, and potential at a predetermined point in the resistance film 35 is monitored to see whether or not the output voltage of booster I or booster II is appropriate.
A 16 Mb DINOR type flash memory employs a boosting and potential measuring configuration as shown in FIG. 4, because 10 V and -8 V must be generated from a supply voltage of 3.3 V generated by an external power supply.
DINOR is an acronym for "divided bit-line NOR type". Details of the configuration of the DINOR type flash memory are found in, for example, "A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY", 1992 IEDM TECHNICAL DIGEST, pp. 599-602 or "A 3.3 V-Only 16 Mb DINOR Flash Memory", 1995 ISSCC DIGEST OF TECHNICAL PAPERS.
Techniques relating to DINOR flash memories are disclosed also in "3.3 V Single Power Supply", Mitsubishi Denki Giho, Vol. 69, No. 3, pp. 47-50 (1995) and "Realization of low-voltage Reloading by F-N Injection, Achievement of both Cost Reduction and Functional Enhancement", NIKKEI MICRODEVICES, pp. 64-68, January, 1993. The DINOR flash memories disclosed in the foregoing papers are characterized by a hierarchical structure provided with bit lines divided into main bit lines and auxiliary bit lines (or sub bit lines).
The raised potential measuring circuit shown in FIG. 4 consumes a large amount of power if a large current flows through the resistance film 35. Flow of a large current through the raised potential measuring circuit indicates current leakage in the booster and, if current leaks from the booster, the booster cannot raise the input voltage to a desired voltage. Therefore, the resistance film 35 must have a high resistance.
Since the material forming the control gate in a DINOR cell is usually also used for forming its associated word line, this material is typically a metal polycide having a high melting point; for example, a tungsten silicide (WSix) film of 100 nm in thickness. A doped polysilicon film of 100 nm in thickness has a very low sheet resistivity of 12 .OMEGA./.quadrature..
FIG. 5 depicts an essential portion of a conventional DINOR type flash memory provided with the raised potential measuring circuit shown in FIG. 4. In FIG. 5, a memory cell region is shown in the right-hand section, and a peripheral circuit region is shown in the left-hand section.
The memory cell region shown in the right-hand section of FIG. 5 will now be described. A p-type well 3 and an n-type well 4 surrounding the p-type well 3 are formed in a region demarcated by an isolating oxide film 2 in the p-type semiconductor substrate 1. A memory cell formed on the surface of the p-type well 3 has a source 5, a drain 6, and a multilayer structure formed in a region between the source 5 and the drain 6 by laminating a tunnel oxide film 7, a floating gate 8, an insulating film 9 and a control gate 10 in that order.
A sub bit line 14 is formed in an interlayer insulating oxide film and is connected to a main bit line, not shown. The floating gate 8 is formed of polysilicon, and the control gate 10 is a two-layer construction formed by depositing a tungsten silicide layer on a polysilicon layer.
The sub bit line 14 is connected to the drain 6 to apply a bit line voltage to the drain 6. A source voltage is applied to the source 7. A control voltage is applied to the control gate 10. A negative voltage or a ground voltage is applied to the p-type well 3. These voltages are used for programming the memory cell, writing data to, erasing data from or reading data from the memory cell.
The peripheral circuit region shown in the left-hand section of FIG. 5 will now be described. A peripheral circuit and a raised voltage measuring circuit are formed in the peripheral circuit region.
The peripheral circuit comprises a plurality of transistors. As shown in FIG. 5, each transistor has a source 21 and a drain 22 formed in a region of the surface of a p-type semiconductor substrate 1 isolated by the isolating oxide film 2. A two-layer structure of a gate insulating oxide film 23 and a gate electrode 24 is formed between the source 21 and the drain 22.
The raised voltage measuring circuit in the peripheral circuit region has a resistance film 35 formed on the isolating oxide film 2, an insulating film 36 (interlayer insulating film) formed on the resistance film 35, and a wiring line 39 formed on the insulating film 36. The wiring line 39 is connected to the resistance film 35 by a contact 42 penetrating the insulating film 36. A booster I is connected to the wiring line 39 to apply a raised voltage to one end of the resistance film 35. A booster II is connected to the other end of the resistance film 35 to apply another voltage to the other end of the resistance film 35. The potential of a predetermined point in an intermediate portion of the resistance film 35 is measured.
The resistance film 35, similarly to the floating gate formed in the memory cell region, is a polysilicon film. The potential measuring circuit illustrated in FIG. 4 is thus formed on the semiconductor substrate 1.
If the resistance film 35 of the raised voltage measuring circuit is formed, for example, of the same material as that of the floating gate 8 of the memory cell region, penetration indicated at 43 in FIG. 6 occurs in the resistance film 35 when forming a via hole for interconnecting a metal wiring line. This is because the floating gate 8 is a thin film of a thickness on the order of 100 nm. Such penetration 43 forms an unnecessary high resistance portion or an unnecessary current path, so that the desired voltage raising operation cannot be achieved.